As the density of semiconductor devices increases and the size of circuit elements becomes smaller, the resistance capacitance (RC) delay time increasingly dominates the circuit performance. To reduce the RC delay, there is a desire to switch from conventional dielectrics to low-k dielectrics. These materials are particularly useful as intermetal dielectrics, IMDs, and as interlayer dielectrics, ILDs. However, low-k materials present problems during processing, especially during the processing of the conductive material used to make interconnects.
The conductive material is typically patterned and etched using high-energy plasma etch processes. In other process schemes, the low-k material is patterned through the application and patterning of photoresist. The low-k material is etched through the photoresist mask, and then the photoresist is removed with a high energy plasma etch process. The low-k materials are susceptible to damage from a plasma etch because they are softer, less chemically stable or more porous, or any combination of these factors. The plasma damage can manifest itself in higher leakage currents, lower breakdown voltages, and changes in the dielectric constant associated with the low-k dielectric material.
FIG. 1 shows a schematic representation of a cross-section of a damascene structure. Dielectric layer 12 has been laid down over wiring level 11. Extending downwards from the trench 15 is a via hole 14. When the structure has been filled with copper, via 14 provides a connection between the two wiring levels. Because of its high diffusivity and its tendency to act as a recombination center in silicon, steps must be taken to ensure that all the copper is confined to the damascene structure. This is conventionally accomplished with a barrier layer 18 that lines the walls of the trench 15 and via hole 14, as illustrated in FIG. 2.
During processing, low-k dielectric surfaces are susceptible to damage. Porous low-k dielectrics, such as porous silica, are particularly susceptible. When surface pores are damaged, processing chemicals may penetrate into the dielectric and raise its dielectric constant. Low-k dielectric damage causes surface roughness of the trench floor 21 and trench wall 23, as shown in FIGS. 1 and 2. This, in turn, means that a much thicker barrier layer 18, FIG. 2, than normal is needed ensure that there are no thin patches through which copper could move. In the absence of the afore-mentioned roughness problem, a barrier layer about 300 Angstroms thick is sufficient to contain the copper whereas, in the presence of a rough trench surface, this has to be increased to at least 500 Angstroms.
As noted above, dielectric damage causes higher leakage currents, lower breakdown voltages, and changes in the dielectric constant associated with the low-k dielectric material. In view of these and other problems, there is a need for improved low-k dielectric manufacturing methods.